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AS5030
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.10 General Data Transmission Timings
Symbol
t0
Parameter
Rising CLK to CS
Conditions
Min
CLK/2
+0
Typ
Max
CLK/2
+50
Units
ns
t1
t2
t3
t4
t5
t6
Chip select to positive edge of CLK
Chip select to drive bus externally
Setup time command bit data valid to
positive edge of CLK
Hold time command bit data valid after
positive edge of CLK
Float time positive edge of CLK for last
command bit to bus float
Bus driving time positive edge of CLK for
last command bit to bus drive
50
0
50
15
CLK/2
+0
CLK/2 +0
ns
ns
ns
ns
ns
ns
t7
Setup time data bit data valid to positive
edge of CLK
CLK/2
+0
CLK/2
+30
ns
t8
t9
t10
t11
t12
t13
Hold time data bit data valid after positive
edge of CLK
Hold time chip select positive edge CLK to
negative edge of chip select
Bus floating time negative edge of chip
select to float bus
Hold time data bit @ write access
data valid to positive edge of CLK
Hold time data bit @ write access
data valid after positive edge of CLK
Bus floating time negative edge of chip
select to float bus
CLK/2
+0
CLK/2
+50
50
15
50
50
ns
ns
ns
ns
ns
ns
t TO
Timeout period in 2-wire mode
(from rising edge of CLK)
20
24
μs
See Figure 5 for the corresponding timing diagram.
www.ams.com/AS5030
Revision 2.4
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